1. Field of the Invention
The present invention relates generally to the deposition of metal on a semiconductor structure, and more specifically to a method of fabricating a semiconductor structure in which metal is deposited to from an improved via connection despite misalignment between via hole and trench pattern.
2. Description of the Related Art
U.S. Pat. No. 4,789,648 issued to M. M Chow et al discloses a method of depositing metal on a semiconductor structure. According to this prior art, a layered structure of insulating material is provided on a semiconductor substrate in which a layer of metallization is formed. The layered insulator structure consists of a etch stop layer sandwiched between lower and upper insulating layers. The etch stop layer has a window. A photoresist layer having a trench pattern is then deposited on the structure and the portion of the upper insulating layer is etched through the trench pattern to form a wire trench. The etching process is continued to etch the portion of the lower insulating layer through the window of the etch stop layer down to the layer of metallization to form a via hole. Metal is then deposited into the via hole and the wire trench to complete a via connection between the metallization and the conductor in the wire trench.
However, if the trench pattern is misaligned with the window of the etch stop layer, the effective contact area of the metal in the via hole and the metal in the wire trench is reduced. Such a reduced contact area is a potential source of failures.
Further, the etch stop layer is exposed to etching gas while the etching process is continued to form the via hole. Therefore, the etch stop layer must be of a material capable of withstanding erosion under the etching gas, and hence the material that forms the wire trench has a high dielectric constant. As a result, the parasitic capacitance between adjacent wire conductors increases to the detriment of high speed performance of semiconductor devices.